1. Field of the Invention
The present invention relates to a router apparatus which switches packets entailing the processing of a packet switching type layer 3 like IP (Internet Protocol), etc., by using an ATM (Asynchronous Transfer Mode, and particularly to a router apparatus for multiplexing plurality transmission paths for one physical port of the ATM switch.
2. Description of the Related Art
An IP (Internet Protocol) switching network which has been proposed by Epsilon Company has been known as a network which enables high-speed IP-packet transmission by using an ATM technique. As shown in FIG. 48, this network includes an IP switch 1 and an IP packets which have been communicated between conventional LAN/IP networks such as Ethernet, FDDI or the like which is connected to the IP switch gateway 2.
In FIG. 48, a network is illustrated as being divided into a layer 2 (base or subordinate) and a layer 3 (enhancement or superordinate), and a heavy line connecting both the layers 2 and 3 represents the shift of processing between the layers. An IP node 4 serving as a router of a LAN? IP network or the like first performs LAN protocol processing of the layer 2 of Ethernet or the like on an arriving packet (datagram), and then performs IP protocol processing of the layer 3 of the superordinate (i.e., enhancement layer 3) on the packet. Subsequently, after a route through which the packet will be transmitted is determined, the processing of the layer 2 is performed again and the packet is transmitted to an adjacent node. In the IP switch gateway 2 of the IP switching network, the processing of the layer 2 and the processing of the layer 3 are also performed on all the packets to be transmitted. The IP switch 1 also performs the processing of the layers 2 and 3, however, packets which are cut through in communications between an IP switch gateway 2 and an IP switch 1 or between IP switches 1 are subjected to only the processing of the layer 2, and then transmitted. In FIG. 48, heavy lines which should be originally illustrated between the layers 2 and 3 are replaced by heavy dotted lines in order to show that the processing of the layer 3 is cut through.
FIG. 49 shows a constitution example of the IP switch 1 and the IP switch gateway 2. The IP switch 1 comprises an ATM switch 11 and an IP controller 12, and it switches ATM cells with the IP switch gateway 2 connected to the physical port of the ATM switch 11 and with an IP node 3 for performing ATM communications. The IP switch gateway 2 comprises plural LAN interfaces 21A, 21B each of which is individually connected to each transmission path of the LAN?IP network connected to the IP node 4, an IP datagram multiplexing/demultiplexing unit 22 for multiplexing/demultiplexing IP packets which are communicated in the LAN interface, an IP processor 23, and an ATM interface 24 which is connected to the physical port of the ATM switch 11. In this constitution, the IP controller 12 of the IP switch 1 and the IP processor 23 of the IP switch gateway 2 perform communication control on IP in cooperation with each other on the basis of a protocol which is called IFMP (Ipsilon Flow Management Protocol). Here, “flow” represents a train of packets which are transmitted from a transmitting side (transmission source) terminal to a transmitted side (transmission destination) terminal, for example. The IP controller 12 controls VC (Virtual Channel) connection in cooperation with the ATM switch 11 on the basis of a protocol which is called GSMP (General Switch Management Protocol).
The communication between the IP switch gateways 2 which are connected to each other through the IP switch 1 will be described with reference to FIG. 50. IP packets A and B which are transmitted from plural IP nodes 4 of the LAN?IP network to the IP switch gateway 2 are serially multiplexed in this order in the IP datagram multiplexing/demultiplexing unit 22. After the multiplexed IP packets are successively subjected to IP processing in the IP processor 23, they are converted to ATM cells in the ATM interface 24 and then transmitted to the IP switch 1. The ATM cells which are transmitted to the IP switch 1 are transmitted to the IP switch gateway 2 serving as a transmitting side, and processed in the ATM interface 24 and the IP processor 23. Thereafter, the ATM cells thus processed are successively synthesized into IP packets in the IP datagram multiplexing/demultiplexing unit 22 and then transmitted to the LAN interface 21 serving as a transmitted side. After receiving all data of the IP packet, each LAN interface 21 individually transmits the IP packet to the transmission path of the LAN?IP network.
In the conventional system, all the IP packets which are transmitted by the IP switch gateway 2 must be processed in the IP processor 23, and thus the amount of communication to be performed in the IP switch gateway 2 is restricted, so that the multiplicity of the communication in the overall system cannot be enhanced.
Further, in the IP switch gateway 2, the IP packet is serially multiplexed and then subjected to the IP processing. Therefore, as shown in FIG. 50, when an IP packet A having a large data amount is transmitted from a transmission path, the processing and the transmission of an IP packet B which is transmitted from another transmission path are greatly delayed. This is a critical drawback in a public network which needs fairness with respect to access.
Still further, when applied to a public network, not only a service of IP packets, but also various services of frame relays, low-speed ATMs, channel emulation, etc are required, however, the IP switch gateway 2 is structurally restricted so that it can support only the service of IP packets and thus the practical use of the network is restricted.